Deep-tech consulting&integrated systems architecture.

RESEARCH

AAPR

Absolute-Address Partial Residency: an inference execution architecture that turns recurring conditional execution relations inside a Dense Transformer into address-keyed reusable information.

Execution relations as reusable information

AAPR does not begin from activation sparsity itself. In the current post-hoc form, a previous activation address acts as the key to a fixed conditional transition mapping, which returns the next execution address set. In compact form: previous activation address → fixed conditional mapping → next execution address set.

Selective computation is a consequence

AAPR does not create sparsity by first predicting future activations with a separate learned sparse predictor, nor does it apply one global static mask to every input. The recorded execution relation identifies where computation is needed next, so selective computation and partial residency emerge from reusing that relation.

Measured PoC

The current PoC uses Gemma 3 4B in NF4 4-bit form and targets MLP down_proj. It selects 80 of 2,560 output channels per layer, or 3.125%, across an L0–12 chained validation. In Steps 40–41, the observed top-1 gap between the recorded transition map and the real-time oracle was zero within the tested scope.

Physical partial execution and residency

In Step 42, only the selected rows were transferred to the GPU and used for the partial multiplication path: 19.2 MB per token, approximately 2.8% of the corresponding full 13-layer row-transfer volume. In Step 43, releasing part of the original down_proj payload from GPU memory reduced measured VRAM from 3,418 MB to 3,260 MB, a 157 MB reduction, while the tested validation answers were preserved.

These figures describe the measured down_proj PoC and should not be interpreted as a 96.875% reduction in total model computation.

Logical existence and physical residency are separate

AAPR treats the complete logical address space and simultaneous physical residency as separate requirements. A weight payload can remain part of the logical model without every payload being resident in high-speed memory at the same time. The Dense Transformer matrix-multiplication primitive itself remains intact; what changes is which execution targets are materialized and kept resident.